Fernando Antônio Pinto Barúqui

Instituição:

Universidade Federal do Rio de Janeiro

Centro:

Centro de Tecnologia

Unidade:

Escola Politécnica

Departamento:

Departamento de Eletrônica/Poli

ORCID:

não disponível no Lattes


Formação:

  • Universidade Federal do Rio de Janeiro

    Engenharia Elétrica | Doutorado | 1995 - 1999

  • Universidade Federal do Rio de Janeiro

    Engenharia Elétrica | Mestrado | 1987 - 1990

  • Universidade Federal do Rio de Janeiro

    Engenharia Eletrônica | Graduação | 1982 - 1986
Laboratórios:
Nenhum laboratório cadastrado
Nuvens de Palavras:
Artigos:

(60.00% artigos com DOI)

Titulo DOI Ano
A Temperature-Aware Analysis of SAR ADCs for Smart Vehicle Applications 10.29292/jics.v13i1.8 2018
Focal-Plane Compression Imager with Increased Quantization Bit Rate and DPCM Error Modeling 2017
ESTIMADOR DA AGRESSIVIDADE DA CAVITAÇÃO EM TURBINAS HIDROELÉTRICAS BASEADO EM MODELAGEM CICLOESTACIONÁRIA 2016
Cavitation Aggressiveness Estimation in Hydro Turbines Based on Cyclostationary Modeling 10.3895/bjic.v3n1.2892 2016
Low-sensitivity recursive Hilbert transformer using switched-current techniques 10.1049/el.2015.0826 2015
Bulk-tuned Gm-C filter using current cancellation 10.1016/j.mejo.2015.05.010 2015
A Fully Differential CMOS Voltage Buffer for Continuous- and Discrete-Time Applications 10.1007/s00034-010-9226-0 2011
Flipped-around multiply-by-two amplifier with unity feedback factor 10.1007/s10470-011-9642-5 2011
Switched-capacitor decimation filter design using time-multiplexing and polyphase decomposition of transfer functions with low denominator orders 10.1016/j.mejo.2009.07.004 2009
Improving sensitivity of direct-form switched-capacitor filters by coinciding pole¿zero pairs 10.1049/iet-cds:20070297 2008
A 0.35 ?m CMOS AM demodulator 10.1007/s10470-008-9207-4 2008
Low-sensitivity IIR switched-capacitor decimation filters using delay lines with staggered T/H stages 2006
Linearly Tunable CMOS OTA with ConstantDynamic Range Using Source DegeneratedCurrent Mirrors 2006
A 48-16MHz CMOS SC Decimation Filter 2002
Efficient design of integrated switched-capacitor decimation filters 2000
Eventos:

(25.00% eventos com DOI)

Titulo DOI Ano
Voltage Regulator with Ellipsoidal Transistors 10.1109/SBCCI60457.2023.10261974 2023
A temperature-aware analysis of latched comparators for smart vehicle applications 10.1145/3109984.3109994 2017
High-linearity zero-voltage switching current memory cell for measurement applications 10.1109/lascas.2016.7451072 2016
Focal-plane image encoder with cascode current mirrors and increased vector quantization bit rate 10.1109/SBCCI.2016.7724059 2016
Very-low-tranconductance CMOS amplifier using multi-tanh bulk-driven input stage with gate-controlled assymetry for Gm-C applications 10.1109/LASCAS.2013.6519035 2013
A new approach for the design of CMOS voltage buffers for switched-capacitor and gm-C filters 2009
Direct-Form SC Filters with Low Frequency Response Sensitivity to the Transfer Function Coefficients 2008
A CMOS AM Demodulator for Instrumentation Applications 2007
IC design of an analog tunable crossover network 2005
Tunable analog loudspeaker crossover network 2003
Power Consumption Estimation in SC Filters 2003
Analog decimator IC in direct-form polyphase structure 2002
CMOS Switched-Capacitor Integrated Filter for Mixed-Signal Video Applications 2000
Efficient IC design of SC decimation filter 1998
Recursive switched-capacitor hilbert trnasformers 1998
Switched-capacitor decimation filter for 0.8um CMOS 1998
A recursive switched-capacitor decimation filter design for 0.8um CMOS technology 1997
Filtro passa baixas decimador de M-bandas a capacitor chaveado usando uma decomposição da função de transferência em funções passa tudo. 1996
Efficient IIR switched-capacitor decimators and interpolators 1996
Stability and active compensation of OTA-C continuous time high frequency filters 1989
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